Generalized ternary simulation of sequential circuits
RAIRO - Theoretical Informatics and Applications - Informatique Théorique et Applications, Volume 28 (1994) no. 3-4, p. 159-186
@article{ITA_1994__28_3-4_159_0,
author = {Seger, C.-J. and Brzozowski, J. A.},
title = {Generalized ternary simulation of sequential circuits},
journal = {RAIRO - Theoretical Informatics and Applications - Informatique Th\'eorique et Applications},
publisher = {EDP-Sciences},
volume = {28},
number = {3-4},
year = {1994},
pages = {159-186},
zbl = {0879.94040},
language = {en},
url = {http://www.numdam.org/item/ITA_1994__28_3-4_159_0}
}

Seger, C.-J.; Brzozowski, J. A. Generalized ternary simulation of sequential circuits. RAIRO - Theoretical Informatics and Applications - Informatique Théorique et Applications, Volume 28 (1994) no. 3-4, pp. 159-186. http://www.numdam.org/item/ITA_1994__28_3-4_159_0/

1. J. H. Anderson and M. G. Gouda, A new explanation of the glitch phenomenon, Acta Informatica, 1991, 28, pp. 297-309. | MR 1101643 | Zbl 0721.94028

2. J. A. Brzozowski and J. C. Ebergen, Recent developments in the design of asynchronous circuits. In J. Demetrovics J. Csirik and F. Gécseg, editors, Proceedings of Fundamentals of Computation Theory, Lecture Notes in Computer Science, Berlin, Germany, August 1989. Springer-Verlag, pp. 78-94. | MR 1033537 | Zbl 0728.94010

3. J. A. Brzozowski and J. C. Ebergen, On the delay-sensitivity of gate networks, IEEE Transactions on Computers, November 1992, 41, pp. 1349-1360. | MR 1195929

4. J. A. Brzozowski and C.-J. H. Seger, A characterization of ternary simulation of gate networks, IEEE Transactions on Computers, November 1987, C-36, 11, pp. 1318-1327. | Zbl 0641.94030

5. J. A. Brzozowski and C.-J. H. Seger, Advances in asynchronous circuit theory part I: Gate and unbounded inertial delay models, Bulletin of the European Association of Theoretical Computer Science, 1990, 42, pp. 198-249. | Zbl 0747.94023

6. J. A. Brzozowski and C.-J. H. Seger, Advances in asynchronous circuit theory part II: Bounded inertial delay models, MOS circuits, design techniques, Bulletin of the European Association of Theoretical Computer Science, 1991, 43, pp. 199-263. | Zbl 0747.94024

7. J. A. Brzozowski and C.-J. H. Seger, Asynchronous Circuits, Springer-Verlag, to appear.

8. J. A. Brzozowski and M. Yoeli, Digital Networks, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, USA, 1976.

9. J. A. Brzozowski and M. Yoeli, On a ternary model of gate networks, IEEE Transactions on Computers, 1979, C-28, 3, pp. 178-184. | MR 523428 | Zbl 0408.94023

10. E. B. Eichelberger, Hazard detection in combinational and sequential switching circuits, IBM Journal of Research and Development, 1965, 9, pp.90-99. | Zbl 0132.37106

11. D. A. Huffman, The synthesis of sequential switching circuits, IRE Transactions on Electronic Computers, 1954, 257, 3, pp. 161-190. | MR 62648 | Zbl 0166.27201

12. D. A. Huffman, The synthesis of sequential switching circuits, IRE Transactions on Electronic Computers, 1954, 257, 4, pp.275-303. | MR 62648 | Zbl 0166.27201

13. Z. Kohavi, Switching and Finite Automata Theory, Second Edition, McGraw-Hill Book Company, NewYork, NewYork, USA, 1978. | MR 411805 | Zbl 0384.94020

14. M. M. Mano, Digital Design, Second Edition, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, USA, 1991.

15. E. J. Mccluskey, Fundamental mode and pulse mode sequential circuits. In C. M. Popplewell, editor, Proceedings of the IFIP Congress 62, Amsterdam, The Netherlands, 1963, IFIP, North-Holland Publishing Company, pp. 725-730.

16. E. J. Mccluskey, Logic Design Principles, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, USA, 1986.

17. C. E. Molnar, T. P. Fang and F. U. Rosenberger, Synthesis of delay-insensitive modules, In H. Fuchs, editor, Proceedings of the 1985 Chapel Hill Conference on VLSI, Rockville, Maryland, USA, 1985. Computer Science Press, pp. 67-86.

18. M. Mukaidono, Regular ternary logic functions - ternary logic functions suitable for treating ambiguity, In Proceedings of the 13th Annual Symposium on Multiple-Valued Logic, Los Angeles, California, USA, May 1983. IEEE, Computer Society Press, pp. 286-291. | Zbl 0563.94019

19. D. E. Muller and W. S. Bartky, A theory of asynchronous circuits, In Proceedings of an International Symposium on the Theory of Switching, Annals of the Computation Laboratory of Harvard University, Cambridge, Massachusetts, USA, 1959. Harvard University, Harvard University Press, pp. 204-243. | MR 114698 | Zbl 0171.37902

20. C. E. Shannon, A symbolic analysis of relay and switching circuits, AIEE Trans., 1938, 57, pp. 713-723.

21. S. H. Unger, Asynchronous Sequential Switching Circuits, Wiley-Interscience, New York, New York, USA, 1969.

22. M. Yoeli and I. Reicher, Synthesis of delay-insensitive circuits based on marked graphs, Technical Report 543, Department of Computer Science, Technion, Haifa, Israel, 1989.

23. M. Yoeli and S. Rinon, Application of ternary algebra to the study of static hazards, Journal of the ACM, 1964, 11, 1, pp. 84-97. | Zbl 0137.33903