The recourse to operation research solutions has strongly increased the performances of scheduling task in the High-Level Synthesis (called hardware compilation). Scheduling a whole program is not possible as too many constraints and objectives interact. We decompose high-level scheduling in three steps. Step 1: Coarse-grain scheduling tries to exploit parallelism and locality of the whole program (in particular in loops, possibly imperfectly nested) with a rough view of the target architecture. This produces a sequence of logical steps, each of which contains a pool of macro-tasks. Step 2: Micro-scheduling maps and schedules each macro-task independently taking into account all peculiarities of the target architecture. This produces a reservation table for each macro-task. Step 3: Fine-grain scheduling refines each logical step by scheduling all its macro-tasks. This paper focuses on the third step. As tasks are modeled as reservation tables, we can express resource constraints using dis-equations (i.e., negations of equations). As most scheduling problems, scheduling tasks with reservation tables to minimize the total duration is NP-complete. Our goal here is to design different strategies and to evaluate them, on practical examples, to see if it is possible to find optimal solution in reasonable time. The first algorithm is based on integer linear programming techniques for scheduling, which we adapt to our specific problem. Our main algorithmic contribution is an exact branch-and-bound algorithm, where each evaluation is accelerated by variant of Dijkstra's algorithm. A simple greedy heuristic is also proposed for comparisons. The evaluation and comparison are done on pieces of scientific applications from the PerfectClub and the HLSynth95 benchmarks. The results demonstrate the suitability of these solutions for high-level synthesis scheduling.

Keywords: scheduling, resource constraints, reservation tables, dis-equations, branch-and-bound, Dijkstra, integer linear programming, high-level synthesis

@article{RO_2007__41_4_427_0, author = {Cherroun, Hadda and Darte, Alain and Feautrier, Paul}, title = {Reservation table scheduling : branch-and-bound based optimization vs. integer linear programming techniques}, journal = {RAIRO - Operations Research - Recherche Op\'erationnelle}, pages = {427--454}, publisher = {EDP-Sciences}, volume = {41}, number = {4}, year = {2007}, doi = {10.1051/ro:2007036}, mrnumber = {2361295}, language = {en}, url = {http://www.numdam.org/articles/10.1051/ro:2007036/} }

TY - JOUR AU - Cherroun, Hadda AU - Darte, Alain AU - Feautrier, Paul TI - Reservation table scheduling : branch-and-bound based optimization vs. integer linear programming techniques JO - RAIRO - Operations Research - Recherche Opérationnelle PY - 2007 SP - 427 EP - 454 VL - 41 IS - 4 PB - EDP-Sciences UR - http://www.numdam.org/articles/10.1051/ro:2007036/ DO - 10.1051/ro:2007036 LA - en ID - RO_2007__41_4_427_0 ER -

%0 Journal Article %A Cherroun, Hadda %A Darte, Alain %A Feautrier, Paul %T Reservation table scheduling : branch-and-bound based optimization vs. integer linear programming techniques %J RAIRO - Operations Research - Recherche Opérationnelle %D 2007 %P 427-454 %V 41 %N 4 %I EDP-Sciences %U http://www.numdam.org/articles/10.1051/ro:2007036/ %R 10.1051/ro:2007036 %G en %F RO_2007__41_4_427_0

Cherroun, Hadda; Darte, Alain; Feautrier, Paul. Reservation table scheduling : branch-and-bound based optimization vs. integer linear programming techniques. RAIRO - Operations Research - Recherche Opérationnelle, Volume 41 (2007) no. 4, pp. 427-454. doi : 10.1051/ro:2007036. http://www.numdam.org/articles/10.1051/ro:2007036/

[1] Constraint Logic Programming, Selected Research. MIT Press (1993). | MR | Zbl

and ,[2] The PERFECT club benchmarks: Effective performance evaluation of supercomputers. Int. J. Supercomput. Appl. 3 (1989) 5-40.

, , , , , , , , , , , , , , , , , , , , , , and ,[3] Slicer: A state synthesizer for intelligent silicon compilation, in Proc. IEEE Int. Conf. Computer Design: VLSI un Computers and Processors. (1987).

and ,[4] Behavioral synthesis, in 33rd Design Automation Conferences (1996).

,[5] Introduction to Algorithms. The MIT Press and McGraw-Hill Book Company (1989). | MR | Zbl

, , and ,[6] Scheduling and Automatic Parallelization. Birkhauser Boston (2000). | MR | Zbl

, , and ,[7] A note on two problems in connexion with graphs. Numerische Monthly 91 (1959) 333-352.

,[8] Synthèse de haut niveau contrôlée par l'utilisateur. Ph.D. thesis, Université Paris VI, January 2004.

,[9] Some efficient solutions to the affine scheduling problem. part II: Multi-dimensional time. Int. J. Parallel Prog. 21 (1992) 389-420. | Zbl

,[10] Scalable and modular scheduling, in Computer Systems: Architectures, Modeling and Simulation (SAMOS 2004), edited by A.D. Pimentel and Vassiliadis. Springer Verlag, Lect. Notes Comput. Sci. 3133 (2004) 433-442.

,[11] Incremental algorithms for the single-source shortest path problem, in Proc. of the 14th Conference on Foundations of Software Technology and Theoretical Computer Science, London, UK, Springer-Verlag (1994) 113-124. | Zbl

, , and ,[12] Introduction to high-level synthesis. IEEE Des. Test Comput. 11 (1994) 44-54.

and ,[13] Principle of Digital Design. Prentice Hall international edition (1997).

,[14] Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis, in 28th Annual ACM/IEEE Design Automation Conference (DAC'91), San Francisco, CA, USA (1991) 2-7.

and ,[15] SPARK: A high-level synthesis framework for applying parallelizing compiler transformations. in VLSID'03: Proc. of the 16th International Conference on VLSI Design (VLSI'03), IEEE Computer Society (2003).

, , , and ,[16] Fundamentals of Computer Algorithms. Computer Science Press (1978). | MR | Zbl

and ,[17] Integer linear programming vs. graph-based methods in code generation. Technical Report A/01/98, Universität des Saarlandes, February 1998.

and ,[18] Constraints-driven scheduling and resource assignment. ACM Trans. Des. Autom. Electron. Syst. 8 (2003) 355-383.

,[19] Scheduling using behavioral templates, in DAC'95: Proc. of the 32nd ACM/IEEE Conference on Design Automation, New York, NY, USA, ACM Press (1995) 101-106.

, , and ,[20] GAUT: An architectural synthesis tool for dedicated signal processors, in EURO-DAC'93, Hambourg, Germany, Sep. 1993, 20-24.

, , , and ,[21] Programmation mathématique : théorie et algorithmes. Dunod, Paris (1983). | Zbl

,[22] Integer and combinatorial optimization. John Wiley & sons, New York (1988). | MR | Zbl

and ,[23] CPLEX Optimization, Using the CPLEX callable library (1995).

[24]

and , 1995 high level synthesis design repository, in ISSS '95: Proc. of the 8th international symposium on System synthesis. New York, NY, USA, ACM Press. (1995) 170-174.[25] MAHA: a program for datapath synthesis, in DAC '86: Proc. of the 23rd ACM/IEEE conference on Design automation. Piscataway, NJ, USA, IEEE Press (1986) 461-466.

, and .[26] An incremental algorithm for a generalization of the shortest-path problem. J. Algorithms, (1992). | MR | Zbl

and ,[27] Iterative modulo scheduling. Int. J. Parallel Prog. 24 (1996) 3-64.

,[28] Theory of Linear and Integer Programming. John Wiley & Sons, Inc., New york (1986). | MR | Zbl

,[29] A two-stage solution approach to multidimensional periodic scheduling. IEEE Trans. Comput.-Aided Des. 20 (2001) 1185-1199.

, , , and ,[30] Scheduling strategies in high-level synthesis. Informatica (Slovenia) 18 (1994).

,[31] Introduction to the scheduling problem. IEEE Des. Test 12 (1995) 60-69.

and ,[32] Introduction to Graph Theory. Prentice Hall (1996). | MR | Zbl

,[33] Pareto-optimization-based run-time task scheduling for embedded systems, in CODES+ISSS'03: Proc. of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (ISSS'03), ACM Press (2003) 120-125.

and ,[34] SILP: Scheduling and Allocating with Integer Linear Programming. Ph.D. thesis, Technische Fakultät der Universität des Saarlandes (1996).

,*Cited by Sources: *